About the Position

Analog Layout Design, Staff Engineer in Hanoi, Viet Nam

At Synopsys, our Hardware Engineers are at the forefront of designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Responsibilities

Working on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees.
Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.
Applying Analog Layout techniques to ensure design meets performance with minimum area and good yield.
Building and enhancing layout flow for faster, higher quality design processes.
Performing layout verification for DRC/LVS/ERC/ANT/ESD/DFM.
Conducting PERC verification for ESD/LUP checks.
Completing all design quality checks and data quality checks.
Collaborating with Place and Route engineers to integrate analog layouts into the top level.
Working with the Package team to ensure the integration of top die and package.
Participating in design reviews across the global team.
Engaging in package design, including interposer and RDL design.
Collaborating closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product.
Joining research programs to implement new ideas for future products and flows.
Leading a layout team to complete a full design block.
Mentoring junior layout engineers or interns.

Requirements

Education: BS in Electronics Engineering, Electromechanics, Telecommunications.
Experience: 5+ years of experience in custom layout.
Tools: Proficiency with layout entry tools: Cadence, Synopsys.
Verification: Experience with layout verification tools: Mentor Calibre, Synopsys ICV.
Knowledge: Understanding of basic semiconductor fabrication processes and MOSFET fundamentals.
Techniques: Knowledge of high-speed layout techniques, ESD, Latchup, Antenna, EMIR.
Mentoring: Experience mentoring/leading junior layout engineers.
Communication: Ability to write layout review presentations and layout verification reports.
Language: Good English communication skills.

Nice to Have

Layout verification reports
Layout review presentations

We Offer

Comprehensive health, wellness, and financial benefits.
Time Away: ETO and FTO Programs.
Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP: Purchase Synopsys common stock at a 15% discount.
Retirement Plans: Save for your future with our retirement plans.
Competitive salaries.

About the Company

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

Hiring Process

Apply: Submit your resume, skills, and experience.
Phone Screen: A recruiter and/or hiring manager will reach out.
Interview: Meet with members of the hiring team.
Offer: Receive a verbal offer followed by a written offer.
Onboarding: Complete new hire documentation.
Welcome: Get acclimated with the help of your manager, team, and a peer buddy.

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Analog Layout Design, Staff Engineer

Job description