Principal Digital Design Engineer (AI Fabric)

About the Position

Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment.

Responsibilities

• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
• Work closely with post-silicon teams to facilitate silicon bring-up and debug.
• Mentor junior engineers to develop their technical skills and expertise.
• Actively contribute to the development and improvement of silicon development processes.
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success.

Requirements

Education & Experience

• Bachelor’s degree in electrical engineering or equivalent.
• 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.

Digital Design Expertise

• Architecture definition and micro-architecture development.
• RTL coding, functional simulation, and synthesis.
• Timing closure and gate-level simulation (GLS).
• Design for test (DFT) implementation.
• Production experience with advanced CMOS nodes (≤7nm).

Protocols & Integration

• Deep expertise in at least one high-speed protocol-PCIe, Ethernet, Infiniband, DDR, or similar.
• Third-party IP integration and verification.
• Block-level design ownership from architecture through GDS.

Tools & Methodologies

• Proficiency with Cadence and/or Synopsys digital design flows.
• Familiarity with UVM-based verification methodologies.
• Silicon bring-up, debug, and failure analysis expertise.

Professional Attributes

• Strong work ethic with the ability to balance multiple priorities in a dynamic environment.
• Excellent communication and collaboration skills; comfortable working cross-functionally with global teams.
• Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements.
• Customer-focused mindset with ability to translate business needs into technical excellence.

Nice to Have

• Track record of delivering multiple high-performance designs to production in data-center environments.
• Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints.
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.).
• Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality.

We Offer

• Competitive base salary range: $185,000.00 USD – $230,000.00 USD.
• Full-time position with on-site presence in San Jose, CA.

About the Company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.