Senior STA Engineer

About the Position

We are seeking a Senior STA Engineer with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to resolve complex timing issues.

Responsibilities

• Own STA and timing signoff activities from synthesis through physical design and tape-out.
• Perform MCMM/MMMC timing analysis across all functional and test modes.
• Analyze and debug setup, hold, recovery, removal, min/max, and clock-related violations.
• Develop, review, and validate SDC constraints, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.
• Perform detailed clock tree and clock timing analysis, including skew, latency, uncertainty, jitter, and clock reconvergence.
• Drive timing closure in collaboration with RTL, synthesis, physical design, and ECO teams.
• Analyze critical timing paths and recommend design, synthesis, placement, routing, or ECO solutions.
• Perform timing analysis considering OCV/AOCV/POCV, derates, SI/crosstalk, and process-voltage-temperature variations.
• Review timing constraints and methodology to ensure signoff-quality timing analysis.
• Support timing ECOs and evaluate their impact across multiple corners and modes.
• Develop and maintain Tcl/Python automation for STA analysis, report generation, and flow optimization.
• Debug complex timing issues and provide technical guidance to junior STA engineers.
• Participate in methodology development, flow improvements, and timing signoff reviews.
• Coordinate with cross-functional teams to ensure project milestones and tape-out schedules are achieved.

Requirements

• Strong expertise in Static Timing Analysis and timing closure.
• Hands-on experience with Synopsys PrimeTime, Cadence Tempus, or equivalent STA tools.
• Excellent knowledge of SDC constraints and timing exceptions.
• Strong understanding of ASIC/SoC design, synthesis, physical design, and signoff flows.
• Expertise in MCMM/MMMC analysis.
• Good understanding of OCV/AOCV/POCV, CPPR, SI/crosstalk, derating, and variation-aware timing.
• Strong knowledge of clock-domain timing, clock uncertainty, skew, latency, and clock reconvergence.
• Proficiency in Tcl scripting; Python/Perl scripting is an advantage.
• Strong debugging, analytical, and problem-solving skills.

Senior-Level Expectations

• Ability to independently own STA for a block or full-chip design.
• Ability to identify root causes of complex timing violations and drive them to closure.
• Ability to interact effectively with design, RTL, synthesis, PD, CTS, and signoff teams.
• Experience mentoring junior engineers and reviewing their STA work.
• Strong ownership, communication, and project-management skills.
• Ability to work in a fast-paced semiconductor environment and deliver against tight tape-out schedules.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.

About the Company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.