Senior/ Staff Package Design Engineer

About the Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, driving the physical implementation strategy for chips that power the world's largest AI clusters.

Responsibilities

• Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
• Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
• Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
• Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
• Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
• Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
• Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
• Support NPI, qualification, and product sustainment activities, including vendor technical reviews

Requirements

• 5+ years of hands-on IC package design experience for high-performance semiconductor products, with full technical ownership from concept through tape-out
• Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and hands-on experience designing complex packages (BGA, FCBGA, FCCSP)
• Strong package integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership
• Deep understanding of signal, power, and thermal integrity at the package level, with the ability to execute design tradeoffs based on analysis
• Proven manufacturing and release experience, including running DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs

Nice to Have

• Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces
• Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)
• Experience supporting chiplet-based architectures and heterogeneous integration
• Demonstrated track record of complete technical package ownership on high-volume products

We Offer

• Competitive salary
• Opportunity to work in a strategic R&D center in Israel
• Collaborative and innovative work environment

About the Company

Astera Labs is committed to fostering a diverse and inclusive workplace. We actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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