Senior Staff Physical Design Engineer

About the Position

Engineer the Future with Us

We currently have 683 open roles

About the Role

Senior Staff Physical Design Engineer

Sunnyvale, California, United States

Base Salary Range: $157,000 - $235,000

Date posted: 09/30/2026

About Synopsys

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

Responsibilities

• Drive timing closure and signoff readiness for advanced-node designs at 5nm, 3nm, and below, working across block, subsystem, and full-chip implementations
• Develop and refine physical design methodologies and automation flows using TCL, Python, and Perl to improve design quality, turnaround time, and predictability
• Perform static timing analysis, clock-tree synthesis, and ECO implementation using PrimeTime, ICC2, Fusion Compiler, and industry-standard signoff tools
• Analyze design data and PPA trends to identify bottlenecks, optimize workflows, and inform next-generation flow development
• Collaborate with cross-functional teams including front-end design, verification, and CAD to ensure successful silicon delivery on schedule
• Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to improve implementation outcomes
• Troubleshoot complex physical design challenges including congestion, power integrity, and multi-corner timing convergence, developing scalable technical solutions that can be reused across projects

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
• 8+ years of hands-on experience in ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level environments
• Deep expertise with industry-standard implementation tools including Synopsys ICC2, Fusion Compiler, or Cadence Innovus
• Strong working knowledge of timing, power, and signoff tools such as PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, or Conformal
• Proven ability to develop design flows, methodologies, and productivity-enhancing automation using TCL, Python, Perl, or similar scripting languages
• Experience with advanced-node semiconductor design at 7nm or below, including leading-edge process technologies and associated design challenges
• Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows is a strong plus

Nice to Have

• Experience with machine learning and AI-assisted design optimization

We Offer

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.

About the Team

Your recruiter will share more about the team structure and mission during the interview process.

About the Company

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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