SeniorFPGA Developer

About the Position

We are seeking a Principal/Staff-level FPGA Engineer with 12-15 years of experience to define and drive FPGA architecture for our state-of-the-art Communications Test & Measurement products. Working for a global provider of network test, monitoring, and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway, you will be a recognized technical authority in your field.

Responsibilities

• Define and drive end-to-end FPGA architecture, including make/buy tradeoffs on IP, floorplanning, and timing closure strategy for multi-gigabit designs.
• Develop DFX approach using Verilog/SystemVerilog/VHDL and industry-leading simulation, synthesis, place-and-route, and formal/UVM verification tools.
• Serve as the final technical escalation point for FPGA design and debug issues across the team.
• Mentor other FPGA engineers and lead root-cause debug of silicon and board bring-up issues.

Requirements

• Must have

  • BS or MS degree in Electrical and/or Computer Engineering.
  • Minimum of 12-15 years of relevant experience, including at least 5+ years specifically architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs.
  • Demonstrated expertise in architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL.
  • Deep, hands-on expertise with FPGA transceivers, hard IP, and PLLs, including timing closure, equalization, and link debug at multi-Gbps rates.
  • Proven experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.6T) and IP protocol stacks in production designs.
  • Proven expertise with optical interfaces and modules (SFPs, QSFPs) in shipped products.
  • Deep working knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP (VoIP, IPTV).
  • Extensive experience with AMD or Altera FPGA devices and their full implementation toolchains, including advanced timing closure and floorplanning techniques.
  • Proven experience with formal verification and/or UVM-based verification methodologies.
  • Demonstrated track record of taking FPGA designs from architecture through volume production, including systems-level tradeoffs across the HW/FW boundary.
  • Version control experience using Git or similar tools.
  • Exceptional written and oral communication skills, including the ability to mentor engineers and communicate architecture decisions with stakeholders across the world.
  • Exceptional analytical and organizational skills, with an uncompromising commitment to accuracy and technical rigor in a fast-paced product environment.

• Nice to have

  • Patents or published work in FPGA architecture, high-speed digital design, or DSP.
  • Experience defining test strategies for multi-Gbps compliance testing.
  • General purpose microprocessor and DSP systems, PCIe, high-speed digital board design, PLL design, and analog signal conditioning experience.
  • Simulation experience using Siemens Questa, Aldec Riviera, or similar tools.
  • Contribution to or deep familiarity with open verification methodologies (e.g., cocotb, UVM community contributions).
  • Utilization of generative AI tools to assist in concept and implementation of FPGA designs.

We Offer

• Remote work from Spain.
• Competitive compensation package.
• Opportunity to work on cutting-edge Communications Test & Measurement products.

About the Company

We are a global provider of network test, monitoring, and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway. A leader in light management technologies for 3D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government, and aerospace applications. Our employees are passionate about supporting customer success and welcome people who bring their best every day to the company – to question, to collaborate, and to push for solutions that will delight our customers.