SOC Engineering, Sr Staff Engineer (STA)

About the Position

SOC Engineering, Sr Staff Engineer (STA)

At Synopsys, our Hardware Engineers are at the forefront of designing and developing cutting-edge semiconductor solutions. They focus on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Responsibilities

• Own and execute block-level Static Timing Analysis (STA) signoff and contribute to full-chip timing closure for advanced process nodes.
• Perform STA debugging and closure, and drive issue resolution with design/PD teams.
• Develop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage.
• Run and analyze power signoff/support flows (PrimePower / PT-PX) and correlate timing/power impacts of ECOs.
• Support timing and power ECO generation, and validate fixes through signoff checks and regressions.
• Work with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, SI awareness, AOCV/POCV, derates).
• Use Synopsys tools such as PrimeTime, PrimePower/PT-PX, PrimeClosure/Tweaker (as applicable) to meet PPA targets.
• Build/maintain automation in TCL/Python/Perl to improve STA productivity, reporting, and regression quality.
• Contribute to improving STA methodologies, checklists, and best practices; mentor junior engineers informally as needed.

Requirements

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field.
• 8+ years of relevant experience in STA / timing closure (block ownership expected; full-chip exposure preferred).
• Strong hands-on experience in:
  • Constraints development/validation (SDC)
  • STA signoff across modes/corners, including MMMC concepts
  • Timing closure debugging and ECO validation
  • Power analysis/support (PrimePower / PT-PX exposure preferred)
• Proficiency with Synopsys tools such as PrimeTime (required); PrimePower/PT-PX, PrimeClosure/Tweaker (preferred).
• Working knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., StarRC), and signoff correlation (preferred).
• Strong scripting skills in TCL (required) and Python/Perl (preferred).
• Understanding of low-power and high-frequency design considerations (UPF awareness is a plus).

Nice to Have

• Exposure to 5nm technology node

We Offer

• Comprehensive range of health, wellness, and financial benefits.
• Competitive salaries.
• Opportunities for professional growth and development.

About the Company

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence-from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

Location

Hyderabad, India

Apply

Interested candidates can apply through our careers page.