Tech Lead STA Engineer

About the Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Tech Lead STA Engineer

Location - Hyderabad, Telangana, India

Experience - 6-14 years

Role Overview

Astera Labs is hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you'll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry.

This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity. Your work directly enables the PCIe, CXL, UALink, and Ethernet platforms that hyperscalers depend on - and you'll have the ownership, influence, and tooling to do the best work of your career.

Responsibilities

• Full-Chip STA Signoff & Timing Closure
• Methodology & Flow Development
• Cross-Functional Technical Leadership
• Mentorship & Technical Strategy

Requirements

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field
• 6+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs
• Proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below)
• Deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development
• Strong understanding of clocking architectures, CDC, OCV/AOCV/POCV, crosstalk, and IR-aware timing
• Proficiency in scripting (Tcl, Python, Perl) for STA flow automation and report analysis

Nice to Have

• Master's degree in Electrical Engineering or related field
• Experience with high-speed connectivity SoCs (PCIe Gen 6/7, CXL, UALink, or Ethernet)
• Familiarity with hierarchical STA, ETM/ILM models, and timing budgeting across large partitions
• Experience with low-power signoff (UPF/CPF), multi-voltage domains, and DVFS timing implications
• Strong cross-functional collaboration and mentorship skills in a fast-paced product environment

We Offer

• Opportunity to work in a hyper-growth company
• Be part of a team that enables the next-generation of AI infrastructure
• Competitive compensation and benefits

About the Company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.