Silicon Engineer

Rewrite Your Future at Capgemini Engineering

Are you a seasoned Silicon engineer ready for your next big challenge? This is your opportunity to transform the semiconductor industry and expand your career internationally by working on large-scale projects with leading players in a dynamic, innovative environment.

Discover the unique opportunities in Eastern Europe’s engineering centers in Romania (Bucharest, Brasov, Cluj, and Iasi), Poland (Krakow), Serbia (Belgrade, Novi Sad, and Nis), and Greece (Thessaloniki).

About the Position

Join Capgemini Engineering as a Silicon Engineer and work on large-scale semiconductor projects in Eastern Europe. With over 20 years of expertise in this field, Capgemini Engineering leverages its deep knowledge to help semiconductor companies bring chips to industry. Our team of 400+ silicon engineers, across 5 countries, is committed to delivering innovative solutions that power the digital world, positioning Silicon Engineering at the heart of our ambition for Intelligent Industry.

Responsibilities

• End-to-End Chip Design: From RTL (Register Transfer Level) to GDSII (Graphic Data System Version II), we provide comprehensive design services, ensuring precision and high performance at every stage.
• Software and Hardware Engineering Services: We prepare chips for development and tailor platforms and products to meet the specific needs of diverse end markets.

Our silicon engineering expertise bridges the gap between industry demands and real-world applications. By integrating cutting-edge technology, deep knowledge, and a collaborative network, our engineers work across key areas including Analog Circuit Design, Digital Circuit Design, Analog Mixed-Signal Verification, Digital Verification, Firmware Development, and Emulation and Laboratory Validation.

Requirements

• CMOS process nodes
• SoC design flows
• Schematic entry
• Simulation
• Spice models
• IC production effects
• UNIX/Linux
• English

Nice to Have

• Experience with state-of-the-art analog design tools
• Experience with different implementation technologies

We Offer

• Relocation support
  • Work permit acquisition
  • Visa and immigration assistance
  • Residency and healthcare
  • Legal and compliance support
• Comprehensive onboarding
  • Personalized integration plan
  • Dedicated onboarding specialist
• Career growth
  • Challenging projects
  • Career development opportunities
  • Mentorship from a global network of experts

About the Company

With over 20 years of expertise in this field, Capgemini Engineering leverages its deep knowledge to help semiconductor companies bring chips to industry. Our team of 400+ silicon engineers, across 5 countries, is committed to delivering innovative solutions that power the digital world, positioning Silicon Engineering at the heart of our ambition for Intelligent Industry.

Partnering with industry giants like Arm and Intel Foundry, our mission is to empower our clients to succeed by delivering top-tier solutions across the entire chip lifecycle.

Opportunities in Eastern Europe

Discover detailed job descriptions, including key responsibilities and required skills. Find the perfect role that matches your expertise and ambitions at Capgemini Engineering and apply now!

• Analog Lead Circuit Design Engineer
• Analog Lead Layout Engineer
• Design-for-Testability (DFT) Senior Engineer
• Design Verification (DV) Senior Engineer
• Physical Design (PD) Senior Engineer
• Register Transfer Level (RTL) Senior Engineer

Analog Lead Circuit Design Engineer

Key responsibilities:

Highly motivated and dynamic engineer able to adopt new technology quickly

Understanding of advanced CMOS process nodes and SoC design flows

Experience with tools for schematic entry, simulation, spice models, and IC production effects

Proficient knowledge of UNIX/Linux and fluent English

M.Sc.EE or equivalent degree in Electronics, Computer Science, or Electrical engineering

Analog Lead Layout Engineer

Key responsibilities:

Experience with state-of-the-art analog design tools

Experience with different implementation technologies

Understanding of advanced CMOS process nodes and SoC design flows

Experience with tools for physical layout, schematic entry, and physical verification

Proficient knowledge of UNIX/Linux and fluent English

M. Sc. EE or equivalent degree in Electronics, Computer Science, or Electrical engineering

Design-for-Testability (DFT) Senior Engineer

Key responsibilities:

Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST

Closely work with the physical design team to resolve timing constraints/issues

Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues

Debug and improve important DFT KPIs: test coverage/pattern efficiency

Hierarchical retargeting

Silicon bring-up, diagnosis, and support for physical failure analysis

Design Verification (DV) Senior Engineer

Key responsibilities:

Own verification of IPs and SoCs in prototype and SoC design environment

Establish functional and performance benchmarks

Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms

IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IPs/SoCs

Hands-on experience using an industry-standard verification methodology (UVM/VMM)

Hands-on experience with Verilog/System Verilog or VHDL skills

Physical Design (PD) Senior Engineer

Key responsibilities:

Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below)

In depth Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning, and analysis, Scan re-ordering, placement, CTS, place, and route

Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing)

In charge of all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis, and fixes

Be part of the overall Low Power solution development and implementation

Develop/enhance timing-related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top level to block level)

Complete multiple design cycles of high complexity with little supervision

Register Transfer Level (RTL) Senior Engineer

Key responsibilities:

Register Transfer Level (RTL) has a multi-lateral spectrum of increasing complexity which involves a deep understanding of cutting-edge designs and technologies, methods, and developing flows and tools as necessary in support of the design process

Own feasibility studies for defining the system architecture, requirements, and external interfaces

Develop microarchitecture and logic design in collaboration with functional leads to deliver design from architecture to tape-out

Perform RTL coding, Lint checks, CDC tests, and creating timing constraint files

Work closely with Synthesis, STA, PD, and DFT teams to meet all functional requirements, performance, power, and area goals

Develop flows and tools as necessary in support of design activities

Apply Now

Apply now to be part of an exciting new chapter in your career. Our team is here to guide you through every step of the process, ensuring a successful relocation to your new role and life at Capgemini Engineering in Eastern Europe. Let us engineer the future, one chip at a time.

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